1. Field of Invention
The present invention relates to an overlay mark and a method for forming the same. More particularly, the present invention relates to an overlay mark with a relatively high contrast comparing to the background and a method for forming the same.
2. Description of Related Art
In the manufacture of integrated circuit, photolithography process is used to transfer patterns from a photo mask having customized circuit patterns to thin films formed on a wafer. The image transfer process comprises steps of forming a photoresist layer on a non-process layer, illuminating the photoresist layer through a photo mask having the customized circuit patterns, developing the photoresist layer and then etching the non-process layer by using the patterned photoresist layer as a mask. Hence, the image transfer process is accomplished. For a well-manufactured integrated circuit product, the image transfer process mentioned above is performed several times to transfer the circuit patterns to each non-process layers to form the electrically circuit device. Therefore, it is important to align the successive patterned layers to reduce the misalignment errors as the critical dimension of the semiconductor device becomes smaller and smaller.
Typically, the overlay correlation set in an exposure tool is used to insure the alignment precision between the successive patterned layers. That is, after the successive patterned layers are formed, a metrology process for determining the precision of the overlay alignment can be performed by referring to the overlay alignment mark sets of the successive patterned layers. FIG. 1A is a top view showing a wafer with a plurality of device regions thereon. FIG. 1B is an enlarge view of a portion of FIG. 1A for illustrating one of the overlay alignment regions of the wafer shown in FIG. 1A. As shown in FIG. 1A together with FIG. 1B, conventionally, in order to achieve proper overlay alignment, at least one overlay mark 106 is formed at the mark region 104 aside the device region 102 on the wafer 100. For each overlay mark 106, there are several sub-marks 106a. Each sub-mark 106a is composed of a fine frame 108 and an alignment component 110 which is encircled by the fine frame 108. Conventionally, the size of the fine frame 108 is smaller than or equal to the size of the spacer (not shown) formed on the device element (not shown) in the device region 102 at the same material level of the fine frame 108. FIG. 1C is a top view showing an overlay mark in a material layer with another overlay mark of another material layer successively formed on the material layer. FIG. 1D is a spectrum showing image contrasts of the conventional overlay marks shown in FIG. 1C. As shown in FIG. 1C and FIG. 1D, after another material layer 114 with an overlay mark 116 is formed on over the wafer 100, a metrology process for determining the precision of the overlay alignment is performed by referring to the overlay alignment mark sets 106 and 116 of the successive material layers 112 and 114. The contrast between the material layer 114 and the background material layer 112 is sharp/intense (as shown in FIG. 1D). However, the surface area of fine frame 108 is only about 0.1% of the sub-mark 106a for single sub-mark 106a. Therefore, the fine frame 108 contributes to a very low image contrast according to the background material layer 112. That is, it is hardly recognize the sub-mark by referring to the fine frame 108. Hence, the metrology process for determining the precision of the overlay alignment between the material layers 112 and 114 by referring to the over layer marks 106 and 116 is hard to be performed since the intense of the overlay mark 106 is so weak that it is hard to recognize the profile and the mark center of each of the sub-marks 106a of the material layer 112. Therefore, the overlay alignment preciseness for the successive patterned layers is poor.